Date on Master's Thesis/Doctoral Dissertation
5-2004
Document Type
Master's Thesis
Degree Name
M.S.
Department
Electrical and Computer Engineering
Committee Chair
Walsh, Kevin Michael, 1955-
Author's Keywords
Applied sciences
Subject
Microfabrication
Abstract
A process for fabricating PMOS transistors and test devices has been developed for educational purposes as part of a microfabrication undergraduate/graduate laboratory course at the University of Louisville. This is to help students from multiple disciplines to understand and perform basic microfabrication processes. Several designs of PMOS devices were fabricated using standard processes such as oxidation, photolithography, diffusion, and sputtering. Process characterization involved testing PMOS transistors, Cross Bridge Kelvin Structures, and Van der Pauw structures. Characterization of PMOS transistors was performed using I-V curves for varying oxide thicknesses (tox) grown using dry oxidation, wet oxidation and RTP (rapid thermal processing). Threshold voltages ranged from 1 volt for the thin RTP gate oxide to over 4 volts for the thicker gate oxide. Threshold voltages (Vth) were also compared to the theoretical values. Van der Pauw structures were used to determine sheet resistance (Rs) & Cross Bridge Kelvin structures for determining contact resistance (Rc). Effects on MOS-capacitors, due to gate oxide thickness, band bending with varying gate voltage and how these factors effect the functioning of transistors have been explained with the results of the fabricated devices.
Recommended Citation
Gowrishetty, Usha R. 1979-, "Design, fabrication and testing of P-channel enhancement mode transistors." (2004). Electronic Theses and Dissertations. Paper 520.
https://doi.org/10.18297/etd/520
