Date on Master's Thesis/Doctoral Dissertation

5-2004

Document Type

Master's Thesis

Degree Name

M.S.

Department

Electrical and Computer Engineering

Committee Chair

Naber, John F., 1961-

Author's Keywords

Applied sciences

Subject

Computer arithmetic; Computer arithmetic and logic units; Computer algorithms

Abstract

This research evaluates an innovative binary adder design and compares it against five standard adder designs. It begins with an algorithmic description of the five standard designs followed by the innovative design. It uses two metrics, speed and size, to establish a fair comparison among the designs and draw conclusions about the performance and usability of the innovative design. The metrics are applied to theory, simulation, and implementation of the adder designs. The latter part of the research draws conclusions from the analysis of these metrics to establish a fair comparison between the innovative and existing designs. The five standard designs are the carry-ripple, carry-complete, carry-lookahead, carry-select, and pyramid. The carry-ripple design is the fundamental and most straight-forward approach to addition. The carry-complete takes the carry-ripple design and adds a signal to detect when the addition is complete. The carry-lookahead design uses some intermediate signals to add multiple bits concurrently. The carry-select design is a brute force approach that allows high speed for a large gate count. Lastly, the pyramid design divides the addition into multiple stages, each calculating a single step of the addition process. The innovative design, called the carry-feedback, works by starting with the addends and iterating towards the solution, something unique from the other designs causing the sum to be latched by the adder. It's innovative approach provides a completion signal, similar to the carry-complete adder. The research comes to the conclusion that the carry-feedback design is noteworthy deserving further attention. The carry-feedback design's performance along with its feature of latching the results and ability to signal completion make it an excellent candidate for asynchronous circuits, an area of continued interest in microprocessors.

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